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Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog

Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog 6th Edition

By: M. Morris R. Mano Michael D. Ciletti
ISBN-10: 0134549899
/ ISBN-13: 9780134529561
Edition: 6th Edition
Language: English
				
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Digital Design With an Introduction to the Verilog HDL, VHDL, and SystemVerilog

Digital Design With an Introduction to the Verilog HDL, VHDL, and SystemVerilog

Contents

Preface

    • MULTIMODAL LEARNING
    • FLEXIBILITY
    • NEW TO THIS EDITION
    • DESIGN METHODOLOGY
    • JUST ENOUGH HDL
    • VERIFICATION
    • HDL CONTENT

Chapter 1 Digital Systems and Binary Numbers

    • CHAPTER OBJECTIVES
    • 1.1 DIGITAL SYSTEMS
    • 1.2 BINARY NUMBERS
    • Practice Exercise 1.1
    • 1.3 NUMBER-BASE CONVERSIONS
    • Practice Exercise 1.2
    • 1.4 OCTAL AND HEXADECIMAL NUMBERS
    • Practice Exercise 1.3
    • Practice Exercise 1.4
    • 1.5 COMPLEMENTS OF NUMBERS
    • Diminished Radix Complement
    • Radix Complement
    • Practice Exercise 1.5
    • Subtraction with Complements
    • Practice Exercise 1.6
    • Practice Exercise 1.7
    • 1.6 SIGNED BINARY NUMBERS
    • Practice Exercise 1.8
    • Practice Exercise 1.9
    • Practice Exercise 1.10
    • Practice Exercise 1.11
    • Practice Exercise 1.12
    • Practice Exercise 1.13
    • Arithmetic Addition
    • Arithmetic Subtraction
    • Practice Exercise 1.14 – Using 2’s complements, find the following sums:
    • 1.7 BINARY CODES
    • Binary-Coded Decimal Code
    • Practice Exercise 1.15
    • BCD Addition
    • Practice Exercise 1.16
    • Decimal Arithmetic
    • Practice Exercise 1.17
    • Other Decimal Codes
    • Gray Code
    • ASCII Character Code
    • Error-Detecting Code
    • Practice Exercise 1.18
    • 1.8 BINARY STORAGE AND REGISTERS
    • Registers
    • Register Transfer
    • 1.9 BINARY LOGIC
    • Definition of Binary Logic
    • Logic Gates
    • PROBLEMS
    • REFERENCES
    • WEB SEARCH TOPICS

Chapter 2 Boolean Algebra and Logic Gates

    • CHAPTER OBJECTIVES
    • 2.1 INTRODUCTION
    • 2.2 BASIC DEFINITIONS
    • 2.3 AXIOMATIC DEFINITION OF BOOLEAN ALGEBRA
    • Two-Valued Boolean Algebra
    • 2.4 BASIC THEOREMS AND PROPERTIES OF BOOLEAN ALGEBRA
    • Duality
    • Basic Theorems
    • Operator Precedence
    • Practice Exercise 2.1
    • Practice Exercise 2.2
    • 2.5 BOOLEAN FUNCTIONS
    • Algebraic Manipulation
    • Complement of a Function
    • Practice Exercise 2.3
    • Practice Exercise 2.4
    • Practice Exercise 2.5
    • Practice Exercise 2.6
    • 2.6 CANONICAL AND STANDARD FORMS
    • Minterms and Maxterms
    • Sum of Minterms
    • Product of Maxterms
    • Conversion between Canonical Forms
    • Practice Exercise 2.7
    • Practice Exercise 2.8
    • Practice Exercise 2.9
    • Standard Forms
    • Practice Exercise 2.10
    • Practice Exercise 2.11
    • Practice Exercise 2.12
    • 2.7 OTHER LOGIC OPERATIONS
    • 2.8 DIGITAL LOGIC GATES
    • Extension to Multiple Inputs
    • Positive and Negative Logic
    • Practice Exercise 2.13
    • Practice Exercise 2.14
    • 2.9 INTEGRATED CIRCUITS
    • Levels of Integration
    • Digital Logic Families
    • Computer-Aided Design of VLSI Circuits
    • PROBLEMS
    • REFERENCES
    • WEB SEARCH TOPICS

Chapter 3 Gate-Level Minimization

    • CHAPTER OBJECTIVES
    • 3.1 INTRODUCTION
    • 3.2 THE MAP METHOD
    • Two-Variable K-Map
    • Three-Variable K-Map
    • Practice Exercise 3.1
    • Practice Exercise 3.2
    • Practice Exercise 3.3
    • Practice Exercise 3.4
    • 3.3 FOUR-VARIABLE K-MAP
    • Practice Exercise 3.5
    • Practice Exercise 3.6
    • Prime Implicants
    • Practice Exercise 3.7
    • Five-Variable K-Map
    • 3.4 PRODUCT-OF-SUMS SIMPLIFICATION
    • Practice Exercise 3.8
    • 3.5 DON’T-CARE CONDITIONS
    • Practice Exercise 3.9
    • 3.6 NAND AND NOR IMPLEMENTATION
    • NAND Circuits
    • Two-Level Implementation
    • Practice Exercise 3.10
    • Multilevel NAND Circuits
    • NOR Implementation
    • Practice Exercise 3.11
    • 3.7 OTHER TWO-LEVEL IMPLEMENTATIONS
    • Nondegenerate Forms
    • AND–OR–INVERT Implementation
    • OR–AND–INVERT Implementation
    • Tabular Summary and Example
    • 3.8 EXCLUSIVE-OR FUNCTION
    • Odd Function
    • Parity Generation and Checking
    • 3.9 HARDWARE DESCRIPTION LANGUAGES (HDLs)
    • Design Encapsulation and Modeling with HDLs
    • Verilog—Design Encapsulation
    • Practice Exercise 3.12 – Verilog
    • VHDL—Design Encapsulation
    • Practice Exercise 3.13 – VHDL
    • Structural (Gate-Level) Modeling
    • Verilog
    • Gate Delays
    • VHDL Packages, Libraries, and Logic Systems
    • 3.10 TRUTH TABLES IN HDLs
    • Verilog—User-Defined Primitives
    • VHDL—Truth Tables
    • PROBLEMS
    • REFERENCES
    • WEB SEARCH TOPICS

Chapter 4 Combinational Logic

    • CHAPTER OBJECTIVES
    • 4.1 INTRODUCTION
    • 4.2 COMBINATIONAL CIRCUITS
    • 4.3 ANALYSIS OF COMBINATIONAL CIRCUITS
    • Practice Exercise 4.1
    • 4.4 DESIGN PROCEDURE
    • Code Conversion Example
    • 4.5 BINARY ADDER–SUBTRACTOR
    • Half Adder
    • Full Adder
    • Practice Exercise 4.2
    • Binary Adder
    • Carry Propagation
    • Practice Exercise 4.3
    • Practice Exercise 4.4
    • Practice Exercise 4.5
    • Binary Subtractor
    • Practice Exercise 4.6
    • Overflow
    • 4.6 DECIMAL ADDER
    • BCD Adder
    • 4.7 BINARY MULTIPLIER
    • 4.8 MAGNITUDE COMPARATOR
    • Practice Exercise 4.7
    • 4.9 DECODERS
    • Practice Exercise 4.8
    • Combinational Logic Implementation
    • 4.10 ENCODERS
    • Priority Encoder
    • 4.11 MULTIPLEXERS
    • Boolean Function Implementation with Multiplexers
    • Practice Exercise 4.9
    • Three-State Gates
    • 4.12 HDL MODELS OF COMBINATIONAL CIRCUITS
    • Gate-Level Modeling
    • Verilog (Primitives)
    • Verilog (Vectors)
    • VHDL (User-Defined Components)
    • Verilog
    • Practice Exercise 4.10 (Verilog)
    • Practice Exercise 4.10 (VHDL)
    • Hierarchical Modeling
    • Verilog
    • VHDL
    • HDL Models of Three-State Gates
    • Verilog (Predefined Buffers and Inverters)
    • VHDL (User-Defined Buffers and Inverters)
    • Practice Exercise 4.11
    • Practice Exercise 4.12—(VHDL)
    • Number Representation
    • Verilog
    • VHDL
    • Verilog
    • VHDL
    • Prctice Exercise 4.13
    • Dataflow Modeling
    • Verilog (Predefined Data Types)
    • Verilog (Predefined Operators)
    • VHDL (Predefined Data Types)
    • VHDL (Vectors, Arrays)
    • VHDL (Predefined Operators, Concurrent Signal Assignment)
    • Verilog
    • VHDL
    • Verilog
    • VHDL
    • Verilog
    • VHDL
    • Verilog (Conditional Operator)
    • VHDL (Conditional Signal Assignment)
    • Verilog
    • VHDL
    • 4.13 BEHAVIORAL MODELING
    • Verilog (Procedural Assignment Statements)
    • VHDL (Process Statements, Variables)
    • Verilog
    • VHDL
    • Verilog (Procedural Statement)
    • VHDL (process, if Statement)
    • Verilog
    • VHDL
    • VHDL (Conditional and Selected Signal Assignments)
    • Verilog (case, casex, casez Statements)
    • VHDL (case Statement)
    • 4.14 WRITING A SIMPLE TESTBENCH
    • 4.15 LOGIC SIMULATION
    • PROBLEMS
    • REFERENCES
    • WEB SEARCH TOPICS

Chapter 5 Synchronous Sequential Logic

    • CHAPTER OBJECTIVES
    • 5.1 INTRODUCTION
    • 5.2 SEQUENTIAL CIRCUITS
    • Practice Exercise 5.1
    • 5.3 STORAGE ELEMENTS: LATCHES
    • SR Latch
    • Practice Exercise 5.2
    • D Latch (Transparent Latch)
    • Practice Exercise 5.3
    • 5.4 STORAGE ELEMENTS: FLIP-FLOPS
    • Edge-Triggered D Flip-Flop
    • Practice Exercise 5.4
    • Other Flip-Flops
    • Characteristic Tables
    • Characteristic Equations
    • Direct Inputs
    • Practice Exercise 5.5
    • 5.5 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
    • State Equations
    • State Table
    • State Diagram
    • Flip-Flop Input Equations
    • Analysis with D Flip-Flops
    • Practice Exercise 5.6
    • Analysis with JK Flip-Flops
    • Practice Exercise 5.7
    • Analysis with T Flip-Flops
    • Mealy and Moore Models of Finite State Machines
    • Practice Exercise 5.8
    • Practice Exercise 5.9
    • Practice Exercise 5.10
    • Practice Exercise 5.11
    • Practice Exercise 5.12
    • Practice Exercise 5.13
    • Practice Exercise 5.14
    • 5.6 SYNTHESIZABLE HDL MODELS OF SEQUENTIAL CIRCUITS
    • Behavioral Modeling with Verilog
    • Practice Exercise 5.15—Verilog
    • Practice Exercise 5.16—Verilog
    • Practice Exercise 5.17—Verilog
    • Practice Exercise 5.18—Verilog
    • Practice Exercise 5.19—Verilog
    • Behavioral Modeling with VHDL
    • Practice Exercise 5.20—VHDL
    • HDL Models of Latches and Flip-Flops
    • Verilog
    • VHDL
    • Practice Exercise 5.21—VHDL
    • Verilog
    • Practice Exercise 5.22—Verilog
    • VHDL
    • Practice Exercise 5.23—VHDL
    • Reset Signals
    • Alternative Models of Flip-Flops
    • Verilog
    • VHDL
    • Verilog
    • VHDL
    • State Diagram-Based HDL Models
    • Verilog
    • VHDL
    • Verilog
    • Practice Exercise 5.24—Verilog
    • VHDL
    • Structural Description of Clocked Sequential Circuits Verilog
    • Verilog
    • VHDL
    • Practice Exercise 5.25—VHDL
    • 5.7 STATE REDUCTION AND ASSIGNMENT
    • State Reduction
    • State Assignment
    • 5.8 DESIGN PROCEDURE
    • Synthesis Using D Flip-Flops
    • Excitation Tables
    • Synthesis Using JK Flip-Flops
    • Synthesis Using T Flip-Flops
    • PROBLEMS
    • REFERENCES
    • WEB SEARCH TOPICS

Chapter 6 Registers and Counters

    • CHAPTER OBJECTIVES
    • 6.1 REGISTERS
    • Register with Parallel Load
    • 6.2 SHIFT REGISTERS
    • Practice Exercise 6.1
    • Serial Transfer
    • Serial Addition
    • Practice Exercise 6.2
    • Universal Shift Register
    • 6.3 RIPPLE COUNTERS
    • Binary Ripple Counter
    • BCD Ripple Counter
    • 6.4 SYNCHRONOUS COUNTERS
    • Binary Counter
    • Up–Down Binary Counter
    • BCD Counter
    • Binary Counter with Parallel Load
    • Practice Exercise 6.3
    • 6.5 OTHER COUNTERS
    • Counter with Unused States
    • Ring Counter
    • Johnson Counter
    • 6.6 HDL MODELS OF REGISTERS AND COUNTERS
    • Shift Register
    • Verilog
    • Verilog
    • VHDL
    • Synchronous Counter
    • Verilog
    • VHDL
    • Ripple Counter
    • Verilog
    • Practice Exercise 6.3 – Verilog
    • VHDL
    • Practice Exercise 6.3 – VHDL
    • PROBLEMS
    • REFERENCES
    • WEB SEARCH TOPICS

Chapter 7 Memory and Programmable Logic

    • CHAPTER OBJECTIVES
    • 7.1 INTRODUCTION
    • 7.2 RANDOM-ACCESS MEMORY
    • Write and Read Operations
    • Memory Description in HDL
    • Verilog
    • Timing Waveforms
    • Types of Memories
    • 7.3 MEMORY DECODING
    • Internal Construction
    • Coincident Decoding
    • Address Multiplexing
    • 7.4 ERROR DETECTION AND CORRECTION
    • Hamming Code
    • Single-Error Correction, Double-Error Detection
    • 7.5 READ-ONLY MEMORY
    • Combinational Circuit Implementation
    • Types of ROMs
    • Combinational PLDs
    • 7.6 PROGRAMMABLE LOGIC ARRAY
    • 7.7 PROGRAMMABLE ARRAY LOGIC
    • 7.8 SEQUENTIAL PROGRAMMABLE DEVICES
    • Xilinx FPGAs
    • Basic Xilinx Architecture
    • Configurable Logic Block (CLB)
    • Distributed RAM
    • Interconnect Resources
    • I/O Block (IOB)
    • Enhancements
    • Xilinx Spartan II FPGAs
    • SPARTAN-6 FPGA Family
    • Xilinx Virtex FPGAs
    • PROBLEMS
    • REFERENCES
    • WEB SEARCH TOPICS

Chapter 8 Design at the Register Transfer Level

    • Chapter Objectives
    • 8.1 INTRODUCTION
    • 8.2 REGISTER TRANSFER LEVEL (RTL) NOTATION
    • 8.3 RTL DESCRIPTIONS
    • VERILOG (Edge- and Level-Sensitive Behaviors)
    • Practice Exercise 8.1–Verilog
    • VHDL (Edge- and Level-Sensitive Processes)
    • Practice Exercise 8.2 – VHDL
    • Operators
    • Verilog
    • Practice Exercise 8.3 – Verilog
    • Practice Exercise 8.4 – Verilog
    • Practice Exercise 8.5 – Verilog
    • VHDL
    • Practice Exercise 8.6 – VHDL
    • Practice Exercise 8.7 – VHDL
    • Loop Statements
    • Verilog
    • Practice Exercise 8.8 – Verilog
    • VHDL
    • Practice Exercise 8.9 – VHDL
    • Verilog
    • VHDL
    • Logic Synthesis with HDLs
    • Verilog
    • VHDL
    • Flowchart for Design
    • 8.4 ALGORITHMIC STATE MACHINES (ASMS)
    • ASM Chart
    • ASM Block
    • Simplifications of an ASM Chart
    • Timing Considerations
    • Practice Exercise 8.10
    • ASMD Chart—The Rosetta Stone of Systematic Design
    • 8.5 DESIGN EXAMPLE (ASMD CHART)
    • ASMD Chart
    • Timing Sequence
    • Practice Exercise 8.11
    • Smart and Effective Controller and Datapath Hardware Design
    • Register Transfer Representation
    • State Table
    • Control Logic
    • 8.6 HDL DESCRIPTION OF DESIGN EXAMPLE
    • RTL Description
    • Verilog
    • VHDL
    • Testing the HDL Description
    • Verilog
    • VHDL
    • Structural Description
    • Verilog
    • Verilog
    • VHDL
    • 8.7 SEQUENTIAL BINARY MULTIPLIER
    • Register Configuration
    • ASMD Chart
    • 8.8 CONTROL LOGIC
    • Sequence Register and Decoder
    • One-Hot Design (One Flip-Flop per State)
    • 8.9 HDL DESCRIPTION OF BINARY MULTIPLIER
    • Verilog
    • VHDL
    • Testing the Multiplier
    • Verilog
    • VHDL
    • Behavioral Description of a Parallel Multiplier
    • Verilog
    • VHDL
    • 8.10 DESIGN WITH MULTIPLEXERS
    • Design Example: Count the Number of Ones in a Register
    • Verilog
    • VHDL
    • Testing the Ones Counter
    • 8.11 RACE-FREE DESIGN (SOFTWARE RACE CONDITIONS)
    • 8.12 LATCH-FREE DESIGN (WHY WASTE SILICON?)
    • 8.13 SYSTEMVERILOG—AN INTRODUCTION
    • New Data types
    • User-Defined Data Types
    • Practice Exercise 8.12
    • Naming Convention
    • Enumerated Types
    • Practice Exercise 8.13 (Enumerated type)
    • Compilation Unit
    • Explicit Behavioral Intent
    • Practice Exercise 8.14
    • Bottom-Testing Loop
    • Operators
    • (case . . . inside)
    • PROBLEMS
    • REFERENCES
    • WEB SEARCH TOPICS

Chapter 9 Laboratory Experiments with Standard ICs and FPGAs

    • 9.1 INTRODUCTION TO EXPERIMENTS
    • 9.2 EXPERIMENT 1: BINARY AND DECIMAL NUMBERS
    • Binary Count
    • Oscilloscope Display
    • BCD Count
    • Output Pattern
    • Other Counts
    • 9.3 EXPERIMENT 2: DIGITAL LOGIC GATES
    • Truth Tables
    • Waveforms
    • Propagation Delay
    • Universal NAND Gate
    • NAND Circuit
    • 9.4 EXPERIMENT 3: SIMPLIFICATION OF BOOLEAN FUNCTIONS
    • Logic Diagram
    • Boolean Functions
    • Complement
    • 9.5 EXPERIMENT 4: COMBINATIONAL CIRCUITS
    • Design Example
    • Majority Logic
    • Parity Generator
    • Decoder Implementation
    • 9.6 EXPERIMENT 5: CODE CONVERTERS
    • Gray Code to Binary
    • 9’s Complementer
    • Seven-Segment Display
    • 9.7 EXPERIMENT 6: DESIGN WITH MULTIPLEXERS
    • Design Specifications
    • 9.8 EXPERIMENT 7: ADDERS AND SUBTRACTORS
    • Half Adder
    • Full Adder
    • Parallel Adder
    • Adder–Subtractor
    • Magnitude Comparator
    • 9.9 EXPERIMENT 8: FLIP-FLOPS
    • SR Latch
    • D Latch
    • Leader–follower Flip-Flop
    • Edge-Triggered Flip-Flop
    • IC Flip-Flops
    • 9.10 EXPERIMENT 9: SEQUENTIAL CIRCUITS
    • Up–Down Counter with Enable
    • State Diagram
    • Design of Counter
    • 9.11 EXPERIMENT 10: COUNTERS
    • Ripple Counter
    • Synchronous Counter
    • Decimal Counter
    • Binary Counter with Parallel Load
    • 9.12 EXPERIMENT 11: SHIFT REGISTERS
    • IC Shift Register
    • Ring Counter
    • Feedback Shift Register
    • Bidirectional Shift Register
    • Bidirectional Shift Register with Parallel Load
    • 9.13 EXPERIMENT 12: SERIAL ADDITION
    • Serial Adder
    • Testing the Adder
    • Serial Adder–Subtractor
    • 9.14 EXPERIMENT 13: MEMORY UNIT
    • IC RAM
    • Testing the RAM
    • ROM Simulator
    • Memory Expansion
    • 9.15 EXPERIMENT 14: LAMP HANDBALL
    • IC Type 74194
    • Logic Diagram
    • Circuit Analysis
    • Playing the Game
    • Counting the Number of Losses
    • Lamp Ping-PongTM
    • 9.16 EXPERIMENT 15: CLOCK-PULSE GENERATOR
    • IC Timer
    • Circuit Operation
    • Clock-Pulse Generator
    • 9.17 EXPERIMENT 16: PARALLEL ADDER AND ACCUMULATOR
    • Block Diagram
    • Control of Register
    • Carry Circuit
    • Detailed Circuit
    • Checking the Circuit
    • Circuit Operation
    • 9.18 EXPERIMENT 17: BINARY MULTIPLIER
    • Block Diagram
    • Control of Registers
    • Multiplication Example
    • Datapath Design
    • Design of Control
    • Checking the Multiplier
    • 9.19 HDL SIMULATION EXPERIMENTS AND RAPID PROTOTYPING WITH FPGAS
    • HDL Supplement to Experiment 1 (Section 9.2)
    • HDL Supplement to Experiment 2 (Section 9.3)
    • HDL Supplement to Experiment 4 (Section 9.5)
    • HDL Supplement to Experiment 5 (Section 9.6)
    • HDL Supplement to Experiment 7 (Section 9.8)
    • HDL Supplement to Experiment 8 (Section 9.9)
    • HDL Supplement to Experiment 9 (Section 9.10)
    • HDL Supplement to Experiment 10 (Section 9.11)
    • HDL Supplement to Experiment 11 (Section 9.12)
    • HDL Supplement to Experiment 13 (Section 9.14)
    • HDL Supplement to Experiment 14 (Section 9.15)
    • HDL Supplement to Experiment 16 (Section 9.17)
    • HDL Supplement to Experiment 17 (Section 9.18)

Chapter 10 Standard Graphic Symbols

    • 10.1 RECTANGULAR-SHAPE SYMBOLS
    • 10.2 QUALIFYING SYMBOLS
    • 10.3 DEPENDENCY NOTATION
    • 10.4 SYMBOLS FOR COMBINATIONAL ELEMENTS
    • 10.5 SYMBOLS FOR FLIP-FLOPS
    • 10.6 SYMBOLS FOR REGISTERS
    • 10.7 SYMBOLS FOR COUNTERS
    • 10.8 SYMBOL FOR RAM
    • PROBLEMS
    • REFERENCES
    • WEB SEARCH TOPICS

Appendix Semiconductors and CMOS Integrated Circuits

    • A.1 COMPLEMENTARY MOS
    • CMOS Characteristics
    • A.2 CMOS TRANSMISSION GATE CIRCUITS
    • A.3 SWITCH-LEVEL MODELING WITH HDL
    • Transmission Gate
    • WEB SEARCH TOPICS

 

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