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Computer Organization and Architecture

Computer Organization and Architecture 11th Edition

By: William Stallings
ISBN-10: 0134997190
/ ISBN-13: 9780135160930
Edition: 11th Edition
Language: English
				
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Contents

Preface

    • What’s New in the Eleventh Edition
    • Support of ACM/IEEE Computer Science and Computer Engineering Curricula
    • Objectives
    • Example Systems
    • Plan of the Text
    • Instructor Support Materials
    • Student Resources
    • Projects and Other Student Exercises
    • Interactive Simulations

About the Author

Acronyms

Part One Introduction

    • Chapter 1 Basic Concepts and Computer Evolution
    • Learning Objectives
    • 1.1 Organization and Architecture
    • 1.2 Structure and Function
    • Function
    • Structure
    • SIMPLE SINGLE-PROCESSOR COMPUTER
    • MULTICORE COMPUTER STRUCTURE
    • EXAMPLES
    • 1.3 The IAS Computer
    • 1.4 Gates, Memory Cells, Chips, and Multichip Modules
    • Gates and Memory Cells
    • Transistors
    • Microelectronic Chips
    • Multichip Module
    • 1.5 The Evolution of the Intel x86 Architecture
    • 1.6 Embedded Systems
    • The Internet of Things
    • Embedded Operating Systems
    • Application Processors versus Dedicated Processors
    • Microprocessors versus Microcontrollers
    • Embedded versus Deeply Embedded Systems
    • 1.7 ARM Architecture
    • ARM Evolution
    • Instruction Set Architecture
    • ARM Products
    • CORTEX-A
    • CORTEX-R
    • CORTEX-M
    • 1.8 Key Terms, Review Questions, and Problems
    • Key Terms
    • Review Questions
    • Problems
    • Chapter 2 Performance Concepts
    • Learning Objectives
    • 2.1 Designing for Performance
    • Microprocessor Speed
    • Performance Balance
    • Improvements in Chip Organization and Architecture
    • 2.2 Multicore, Mics, and GPGPUs
    • 2.3 Two Laws that Provide Insight: Ahmdahl’s Law and Little’s Law
    • Amdahl’s Law
    • Little’s Law
    • 2.4 Basic Measures of Computer Performance
    • Clock Speed
    • Instruction Execution Rate
    • 2.5 Calculating the Mean
    • Arithmetic Mean
    • Harmonic Mean
    • Geometric Mean
    • 2.6 Benchmarks and Spec
    • Benchmark Principles
    • SPEC Benchmarks
    • 2.7 Key Terms, Review Questions, and Problems
    • Key Terms
    • Review Questions
    • Problems

Part Two The Computer System

    • Chapter 3 A Top-Level View of Computer Function and Interconnection
    • Learning Objectives
    • 3.1 Computer Components
    • 3.2 Computer Function
    • Instruction Fetch and Execute
    • Interrupts
    • INTERRUPTS AND THE INSTRUCTION CYCLE
    • MULTIPLE INTERRUPTS
    • I/O Function
    • 3.3 Interconnection Structures
    • 3.4 Bus Interconnection
    • 3.5 Point-to-Point Interconnect
    • QPI Physical Layer
    • QPI Link Layer
    • QPI Routing Layer
    • QPI Protocol Layer
    • 3.6 PCI Express
    • PCI Physical and Logical Architecture
    • PCIe Physical Layer
    • PCIe Transaction Layer
    • ADDRESS SPACES AND TRANSACTION TYPES
    • TLP PACKET ASSEMBLY
    • PCIe Data Link Layer
    • DATA LINK LAYER PACKETS
    • TRANSACTION LAYER PACKET PROCESSING
    • 3.7 Key Terms, Review Questions, and Problems
    • Key Terms
    • Review Questions
    • Problems
    • Chapter 4 The Memory Hierarchy: Locality and Performance
    • Learning Objectives
    • 4.1 Principle Of Locality
    • 4.2 Characteristics Of Memory Systems
    • 4.3 The Memory Hierarchy
    • Cost and Performance Characteristics
    • Typical Members of the Memory Hierarchy
    • The IBM z13 Memory Hierarchy
    • Design Principles for a Memory Hierarchy
    • 4.4 Performance Modeling Of A Multilevel Memory Hierarchy
    • Two-Level Memory Access
    • OPERATION OF TWO-LEVEL MEMORY
    • PERFORMANCE
    • Multilevel Memory Access2
    • 4.5 Key Terms, Review Questions, and Problems
    • Key Terms
    • Review Questions
    • Problems
    • Chapter 5 Cache Memory
    • Learning Objectives
    • 5.1 Cache Memory Principles
    • 5.2 Elements of Cache Design
    • Cache Addresses
    • Cache Size
    • Logical Cache Organization
    • Direct Mapping
    • CONTENT-ADDRESSABLE MEMORY
    • ASSOCIATIVE MAPPING
    • SET-ASSOCIATIVE MAPPING
    • Replacement Algorithms
    • Write Policy
    • Line Size
    • Number of Caches
    • MULTILEVEL CACHES
    • UNIFIED VERSUS SPLIT CACHES
    • Inclusion Policy
    • 5.3 Intel x86 Cache Organization
    • 5.4 The IBM z13 Cache Organization
    • 5.5 Cache Performance Models6
    • Cache Timing Model
    • Design Option for Improving Performance
    • 5.6 Key Terms, Review Questions, and Problems
    • Key Terms
    • Review Questions
    • Problems
    • Chapter 6 Internal Memory
    • Learning Objectives
    • 6.1 Semiconductor Main Memory
    • Organization
    • DRAM and SRAM
    • DYNAMIC RAM
    • STATIC RAM
    • SRAM VERSUS DRAM
    • Types of ROM
    • Chip Logic
    • Chip Packaging
    • Module Organization
    • Interleaved Memory
    • 6.2 Error Correction
    • 6.3 DDR DRAM
    • Synchronous DRAM
    • DDR SDRAM
    • 6.4 Edram
    • IBM z13 eDRAM Cache Structure
    • Intel Core System Cache Structure
    • 6.5 Flash Memory
    • Operation
    • NOR and NAND Flash Memory
    • 6.6 Newer Nonvolatile Solid-State Memory Technologies
    • STT-RAM
    • PCRAM
    • ReRAM
    • 6.7 Key Terms, Review Questions, and Problems
    • Key Terms
    • Review Questions
    • Problems
    • Chapter 7 External Memory
    • Learning Objectives
    • 7.1 Magnetic Disk
    • Magnetic Read and Write Mechanisms
    • Data Organization and Formatting
    • Physical Characteristics
    • Disk Performance Parameters
    • SEEK TIME
    • LATENCY TIME
    • TRANSFER TIME
    • A TIMING COMPARISON
    • 7.2 RAID
    • RAID Level 0
    • RAID 0 FOR HIGH DATA TRANSFER CAPACITY
    • RAID 0 FOR HIGH I/O REQUEST RATE
    • RAID Level 1
    • RAID Level 2
    • RAID Level 3
    • REDUNDANCY
    • PERFORMANCE
    • RAID Level 4
    • RAID Level 5
    • RAID Level 6
    • 7.3 Solid State Drives
    • SSD Compared to HDD
    • SSD Organization
    • Practical Issues
    • 7.4 Optical Memory
    • Compact Disk
    • CD-ROM
    • CD RECORDABLE
    • CD REWRITABLE
    • Digital Versatile Disk
    • High-​Definition Optical Disks
    • 7.5 Magnetic Tape
    • 7.6 Key Terms, Review Questions, and Problems
    • Key Terms
    • Review Questions
    • Problems
    • Chapter 8 Input/Output
    • Learning Objectives
    • 8.1 External Devices
    • Keyboard/Monitor
    • Disk Drive
    • 8.2 I/O Modules
    • Module Function
    • I/O Module Structure
    • 8.3 Programmed I/O
    • Overview of Programmed I/O
    • I/O Commands
    • I/O Instructions
    • 8.4 Interrupt-​Driven I/O
    • Interrupt Processing
    • Design Issues
    • Intel 82C59A Interrupt Controller
    • The Intel 8255A Programmable Peripheral Interface
    • ARCHITECTURE AND OPERATION
    • KEYBOARD/DISPLAY EXAMPLE
    • 8.5 Direct Memory Access
    • Drawbacks of Programmed and Interrupt-​Driven I/O
    • DMA Function
    • Intel 8237A DMA Controller
    • 8.6 Direct Cache Access
    • DMA Using Shared Last-​Level Cache
    • XEON MULTICORE PROCESSOR
    • DMA USE OF THE CACHE
    • Cache-​Related Performance Issues
    • Direct Cache Access Strategies
    • Direct Data I/O
    • PACKET INPUT
    • PACKET OUTPUT
    • 8.7 I/O Channels and Processors
    • The Evolution of the I/O Function
    • Characteristics of I/O Channels
    • 8.8 External Interconnection Standards
    • Universal Serial Bus (USB)
    • FireWire Serial Bus
    • Small Computer System Interface (SCSI)
    • Thunderbolt
    • InfiniBand
    • PCI Express
    • SATA
    • Ethernet
    • Wi-​Fi
    • 8.9 IBM z13 I/O Structure
    • Channel Structure
    • I/O System Organization
    • 8.10 Key Terms, Review Questions, and Problems
    • Key Terms
    • Review Questions
    • Problems
    • Chapter 9 Operating System Support
    • Learning Objectives
    • 9.1 Operating System Overview
    • Operating System Objectives and Functions
    • THE OPERATING SYSTEM AS A USER/COMPUTER INTERFACE
    • THE OPERATING SYSTEM AS RESOURCE MANAGER
    • Types of Operating Systems
    • EARLY SYSTEMS
    • SIMPLE BATCH SYSTEMS
    • MULTIPROGRAMMED BATCH SYSTEMS
    • TIME-SHARING SYSTEMS
    • 9.2 Scheduling
    • Long-​Term Scheduling
    • Medium-​Term Scheduling
    • Short-​Term Scheduling
    • PROCESS STATES
    • SCHEDULING TECHNIQUES
    • 9.3 Memory Management
    • Swapping
    • Partitioning
    • Paging
    • Virtual Memory
    • DEMAND PAGING
    • PAGE TABLE STRUCTURE
    • Translation Lookaside Buffer
    • Segmentation
    • 9.4 Intel x86 Memory Management
    • Address Spaces
    • Segmentation
    • Paging
    • 9.5 ARM Memory Management
    • Memory System Organization
    • Virtual Memory Address Translation
    • Memory-​Management Formats
    • Access Control
    • 9.6 Key Terms, Review Questions, and Problems
    • Key Terms
    • Review Questions
    • Problems

Part Three Arithmetic and Logic

    • Chapter 10 Number Systems
    • Learning Objectives
    • 10.1 The Decimal System
    • 10.2 Positional Number Systems
    • 10.3 The Binary System
    • 10.4 Converting Between Binary and Decimal
    • Integers
    • Fractions
    • 10.5 Hexadecimal Notation
    • 10.6 Key Terms and Problems
    • Key Terms
    • Problems
    • Chapter 11 Computer Arithmetic
    • Learning Objectives
    • 11.1 The Arithmetic and Logic Unit
    • 11.2 Integer Representation
    • Sign-Magnitude Representation
    • Twos Complement Representation
    • Range Extension
    • Fixed-Point Representation
    • 11.3 Integer Arithmetic
    • Negation
    • Addition and Subtraction
    • Multiplication
    • UNSIGNED INTEGERS
    • TWOS COMPLEMENT MULTIPLICATION
    • Division
    • 11.4 Floating-Point Representation
    • Principles
    • IEEE Standard for Binary Floating-Point Representation
    • 11.5 Floating-Point Arithmetic
    • Addition and Subtraction
    • Multiplication and Division
    • Precision Considerations
    • GUARD BITS
    • ROUNDING
    • IEEE Standard for Binary Floating-Point Arithmetic
    • INFINITY
    • QUIET AND SIGNALING NANS
    • SUBNORMAL NUMBERS
    • 11.6 Key Terms, Review Questions, and Problems
    • Key Terms
    • Review Questions
    • Problems
    • Chapter 12 Digital Logic
    • Learning Objectives
    • 12.1 Boolean Algebra
    • The Algebra of Sets
    • Boolean Identities
    • 12.2 Gates
    • 12.3 Combinational Circuits
    • Implementation of Boolean Functions
    • ALGEBRAIC SIMPLIFICATION
    • KARNAUGH MAPS
    • THE QUINE-MCCLUSKEY METHOD
    • NAND AND NOR IMPLEMENTATIONS
    • Multiplexers
    • Decoders
    • Read-​Only Memory
    • Adders
    • 12.4 Sequential Circuits
    • Flip-​Flops
    • The S—R LATCH
    • CLOCKED S-R FLIP-FLOP
    • D FLIP-FLOP
    • J-K FLIP-FLOP
    • Registers
    • PARALLEL REGISTERS
    • SHIFT REGISTER
    • Counters
    • RIPPLE COUNTER
    • SYNCHRONOUS COUNTERS
    • 12.5 Programmable Logic Devices
    • Programmable Logic Array
    • Field-​Programmable Gate Array
    • 12.6 Key Terms and Problems
    • Key Terms
    • Problems

Part Four Instruction Sets and Assembly Language

    • Chapter 13 Instruction Sets: Characteristics and Functions
    • Learning Objectives
    • 13.1 Machine Instruction Characteristics
    • Elements of a Machine Instruction
    • Instruction Representation
    • Instruction Types
    • Number of Addresses
    • Instruction Set Design
    • 13.2 Types of Operands
    • Numbers
    • Characters
    • Logical Data
    • 13.3 Intel x86 and ARM Data Types
    • x86 Data Types
    • ARM Data Types
    • ENDIAN SUPPORT
    • 13.4 Types of Operations
    • Data Transfer
    • Arithmetic
    • Logical
    • Conversion
    • Input/Output
    • System Control
    • Transfer of Control
    • BRANCH INSTRUCTIONS
    • SKIP INSTRUCTIONS
    • PROCEDURE CALL INSTRUCTIONS
    • 13.5 Intel x86 and ARM Operation Types
    • x86 Operation Types
    • CALL/RETURN INSTRUCTIONS
    • MEMORY MANAGEMENT
    • STATUS FLAGS AND CONDITION CODES
    • X86 SIMD INSTRUCTIONS
    • ARM Operation Types
    • CONDITION CODES
    • 13.6 Key Terms, Review Questions, and Problems
    • Key Terms
    • Review Questions
    • Problems
    • Appendix 13A Little-, Big-, and Bi-Endian
    • Byte Ordering
    • Bit Ordering
    • Chapter 14 Instruction Sets: Addressing Modes and Formats
    • Learning Objectives
    • 14.1 Addressing Modes
    • Immediate Addressing
    • Direct Addressing
    • Indirect Addressing
    • Register Addressing
    • Register Indirect Addressing
    • Displacement Addressing
    • Relative Addressing
    • Base-Register Addressing
    • Indexing
    • Stack Addressing
    • 14.2 x86 and ARM Addressing Modes
    • x86 Addressing Modes
    • ARM Addressing Modes
    • LOAD/STORE ADDRESSING
    • DATA PROCESSING INSTRUCTION ADDRESSING
    • BRANCH INSTRUCTIONS
    • LOAD/STORE MULTIPLE ADDRESSING
    • 14.3 Instruction Formats
    • Instruction Length
    • Allocation of Bits
    • PDP-8
    • PDP-10
    • Variable-​Length Instructions
    • PD-11
    • VAX
    • 14.4 x86 and ARM Instruction Formats
    • x86 Instruction Formats
    • ARM Instruction Formats
    • IMMEDIATE CONSTANTS
    • THUMB INSTRUCTION SET
    • THUMB-2 INSTRUCTION SET
    • 14.5 Key Terms, Review Questions, and Problems
    • Key Terms
    • Review Questions
    • Problems
    • Chapter 15 Assembly Language and Related Topics
    • Learning Objectives
    • 15.1 Assembly Language Concepts
    • 15.2 Motivation For Assembly Language Programming
    • 15.3 Assembly Language Elements
    • Statements
    • LABEL
    • MNEMONIC
    • OPERAND(S)
    • COMMENT
    • Pseudo-instructions
    • Macro Definitions
    • Directives
    • System Calls
    • 15.4 EXAMPLES
    • Greatest Common Divisor
    • Prime Number Program
    • String Manipulation
    • STRING CONSTANTS AND OPERATIONS
    • MOVING A STRING
    • 15.5 Types of assemblers
    • 15.6 Assemblers
    • Two-Pass Assembler
    • FIRST PASS
    • SECOND PASS
    • ZEROTH PASS
    • One-Pass Assembler
    • Example: Prime Number Program
    • 15.7 Loading and Linking
    • Relocation
    • Loading
    • ABSOLUTE LOADING
    • RELOCATABLE LOADING
    • DYNAMIC RUN-TIME LOADING
    • Linking
    • LINKAGE EDITOR
    • DYNAMIC LINKER
    • 15.8 Key Terms, Review Questions, and Problems
    • Key Terms
    • Review Questions
    • Problems

Part Five The Central Processing Unit

    • Chapter 16 Processor Structure and Function
    • Learning Objectives
    • 16.1 Processor Organization
    • 16.2 Register Organization
    • User-Visible Registers
    • Control and Status Registers
    • Example Microprocessor Register Organizations
    • 16.3 Instruction Cycle
    • The Indirect Cycle
    • Data Flow
    • 16.4 Instruction Pipelining
    • Pipelining Strategy
    • Pipeline Performance
    • Pipeline Hazards
    • RESOURCE HAZARDS
    • DATA HAZARDS
    • CONTROL HAZARDS
    • Dealing with Branches
    • MULTIPLE STREAMS
    • PREFETCH BRANCH TARGET
    • LOOP BUFFER
    • BRANCH PREDICTION
    • DELAYED BRANCH
    • Intel 80486 Pipelining
    • 16.5 Processor Organization for Pipelining
    • 16.6 The x86 Processor Family
    • Register Organization
    • EFLAGS REGISTER
    • CONTROL REGISTERS
    • MMX REGISTERS
    • Interrupt Processing
    • INTERRUPTS AND EXCEPTIONS
    • INTERRUPT VECTOR TABLE
    • INTERRUPT HANDLING
    • 16.7 The ARM Processor
    • Processor Organization
    • Processor Modes
    • Register Organization
    • GENERAL-PURPOSE REGISTERS
    • PROGRAM STATUS REGISTERS
    • Interrupt Processing
    • 16.8 Key Terms, Review Questions, and Problems
    • Key Terms
    • Review Questions
    • Problems
    • Chapter 17 Reduced Instruction Set Computers
    • Learning Objectives
    • 17.1 Instruction Execution Characteristics
    • Operations
    • Operands
    • Procedure Calls
    • Implications
    • 17.2 The Use of a Large Register File
    • Register Windows
    • Global Variables
    • Large Register File versus Cache
    • 17.3 Compiler-​Based Register Optimization
    • 17.4 Reduced Instruction Set Architecture
    • Why CISC
    • Characteristics of Reduced Instruction Set Architectures
    • CISC versus RISC Characteristics
    • 17.5 Risc Pipelining
    • Pipelining with Regular Instructions
    • Optimization of Pipelining
    • DELAYED BRANCH
    • DELAYED LOAD
    • LOOP UNROLLING
    • 17.6 MIPS R4000
    • Instruction Set
    • Instruction Pipeline
    • 17.7 SPARC
    • SPARC Register Set
    • Instruction Set
    • Instruction Format
    • 17.8 Processor Organization For Pipelining
    • 17.9 CISC, RISC, And Contemporary Systems
    • 17.10 Key Terms, Review Questions, and Problems
    • Key Terms
    • Review Questions
    • Problems
    • Chapter 18 Instruction-Level Parallelism and Superscalar Processors
    • Learning Objectives
    • 18.1 Overview
    • Superscalar versus Superpipelined
    • Constraints
    • TRUE DATA DEPENDENCY
    • PROCEDURAL DEPENDENCIES
    • RESOURCE CONFLICT
    • 18.2 Design Issues
    • Instruction-Level Parallelism and Machine Parallelism
    • Instruction Issue Policy
    • IN-ORDER ISSUE WITH IN-ORDER COMPLETION
    • IN-ORDER ISSUE WITH OUT-OF-ORDER COMPLETION
    • OUT-OF-ORDER ISSUE WITH OUT-OF-ORDER COMPLETION
    • Register Renaming
    • Machine Parallelism
    • Branch Prediction
    • Superscalar Execution
    • Superscalar Implementation
    • 18.3 Intel Core Microarchitecture
    • Front End
    • BRANCH PREDICTION UNIT
    • INSTRUCTION FETCH AND PREDECODE UNIT
    • INSTRUCTION QUEUE AND DECODE UNIT
    • Out-of-Order Execution Logic
    • ALLOCATE
    • REGISTER RENAMING
    • MICRO-OP QUEUING
    • MICRO-OP SCHEDULING AND DISPATCHING
    • Integer and Floating-Point Execution Units
    • 18.4 ARM Cortex-A8
    • Instruction Fetch Unit
    • Instruction Decode Unit
    • Integer Execute Unit
    • SIMD and Floating-Point Pipeline
    • 18.5 ARM Cortex-M3
    • Pipeline Structure
    • Dealing with Branches
    • 18.6 Key Terms, Review Questions, and Problems
    • Key Terms
    • Review Questions
    • Problems
    • Chapter 19 Control Unit Operation and Microprogrammed Control
    • Learning Objectives
    • 19.1 Micro-​Operations
    • The Fetch Cycle
    • The Indirect Cycle
    • The Interrupt Cycle
    • The Execute Cycle
    • The Instruction Cycle
    • 19.2 Control of the Processor
    • Functional Requirements
    • Control Signals
    • A Control Signals Example
    • Internal Processor Organization
    • The Intel 8085
    • 19.3 Hardwired Implementation
    • Control Unit Inputs
    • Control Unit Logic
    • 19.4 Microprogrammed Control
    • Microinstructions
    • Microprogrammed Control Unit
    • Wilkes Control
    • Advantages and Disadvantages
    • 19.5 Key Terms, Review Questions, and Problems
    • Key Terms
    • Review Questions
    • Problems

Part Six Parallel Organization

    • Chapter 20 Parallel Processing
    • Learning Objectives
    • 20.1 Multiple Processor Organizations
    • Types of Parallel Processor Systems
    • Parallel Organizations
    • 20.2 Symmetric Multiprocessors
    • Organization
    • Multiprocessor Operating System Design Considerations
    • 20.3 Cache Coherence and the MESI Protocol
    • Software Solutions
    • Hardware Solutions
    • DIRECTORY PROTOCOLS
    • SNOOPY PROTOCOLS
    • The MESI Protocol
    • READ MISS
    • READ HIT
    • WRITE MISS
    • WRITE HIT
    • MESI SIGNALING
    • L1-L2 CACHE CONSISTENCY
    • 20.4 Multithreading and Chip Multiprocessors
    • Implicit and Explicit Multithreading
    • Approaches to Explicit Multithreading
    • 20.5 Clusters
    • Cluster Configurations
    • 20.6 Nonuniform Memory Access
    • Motivation
    • Organization
    • NUMA Pros and Cons
    • 20.7 Key Terms, Review Questions, and Problems
    • Key Terms
    • Review Questions
    • Problems
    • Chapter 21 Multicore Computers
    • Learning Objectives
    • 21.1 Hardware Performance Issues
    • Increase in Parallelism and Complexity
    • Power Consumption
    • 21.2 Software Performance Issues
    • Software on Multicore
    • Application Example: Valve Game Software
    • 21.3 Multicore Organization
    • Levels of Cache
    • Simultaneous Multithreading
    • 21.4 Heterogeneous Multicore Organization
    • Different Instruction Set Architectures
    • CPU/GPU MULTICORE
    • CPU/DSP MULTICORE
    • Equivalent Instruction Set Architectures
    • A7 AND A15 CHARACTERISTICS
    • SOFTWARE PROCESSING MODELS
    • Cache Coherence and the MOESI Model
    • 21.5 INTEL Core i7-5960X
    • 21.6 ARM Cortex-​A15 MPCore
    • Interrupt Handling
    • Cache Coherency
    • L1 CACHE COHERENCY
    • L2 Cache Coherency
    • 21.7 IBM z13 Mainframe
    • Organization
    • Cache Structure
    • 21.8 Key Terms, Review Questions, and Problems
    • Key Terms
    • Review Questions
    • Problems

Appendix A System Buses

    • A.1 Bus Structure
    • A.2 Multiple-Bus Hierarchies
    • A.3 Elements of Bus Design
    • Bus Types
    • Method of Arbitration
    • Timing

Appendix B Victim Cache Strategies

    • B.1 Victim Cache
    • B.2 Selective Victim Cache
    • Incoming Blocks from Memory
    • Swap Between Direct-Mapped Cache and Victim Cache

Appendix C Interleaved Memory

Appendix D The International Reference Alphabet

Appendix E Stacks

    • E.1 Stacks
    • E.2 Stack Implementation
    • E.3 Expression Evaluation

Appendix F Recursive Procedures

    • F.1 Recursion
    • F.2 Activation Tree Representation
    • Fibonacci Numbers
    • Ackermann’s Function
    • F.3 Stack Implementation
    • F.4 Recursion And Iteration

Appendix G Additional Instruction Pipeline Topics

    • G.1 Pipeline Reservation Tables
    • Reservation Tables for Dynamic Pipelines
    • Instruction Pipeline Example
    • G.2 Reorder Buffers
    • In-Order Completion
    • Out-of-Order Completion
    • G.3 Tomasulo’s Algorithm
    • G.4 Scoreboarding
    • Scoreboard Operation
    • Scoreboard Example

Glossary

References

    • Abbreviations

Supplemental Materials

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